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PULSUS
PS9702B
6Ch, 24bit, 192kHz Digital Audio Processor for Full Digital Amplifier
Introduction
The PS9702B is a highly integrated system-on-chip solution for multi-channel AV systems. The PS9702B is 6 channel PCM to PWM modulator with sample rate converter and pre-amplifier functions. It features six 24-bit audio digital-to-digital converters and over-sampling digital filters, a sample rate converter, an audio DSP that functions as an on-chip pre-amplifier with equalizer, volume control, bass management, and compressor functions. The PS9702B accepts industry-standard audio data formats with 16- to 24-bit audio data. Sampling rates of up to 192 kHz are supported. Digital Filter and Sample-rate-converter Section On chip Sample rate converter On chip Digital De-emphasis filter for CD input signal Preamplifier Section Input mixing function Microphone mixing function Stereo REC output Parametric EQ (4 band, 1dB/step) per channel Tone control (15dB, 1dB/step) per channel Bass management function Volume control (+24 ~ -70dB, 0.5dB/step) per channel Dynamic range compression function Soft and Hard Mute Functions PCM-to-PWM modulator section 6 channel PWM Amplification output 95 dB Dynamic Range (typical)
Features
General 1 serial input port for 6Ch and 3 serial input ports for 2Ch (or 2 serial input ports for 6Ch) SPDIF receiver for 2Ch non-encoded PCM input Supports 16/18/20/24 bit Input Supports 32kHz~192kHz Input Sample Rate I2C or SPI control bus 100 pin QFP Package 3.3V Single Power Supply
Application
DVD Receiver (DVD player plus 5.1ch Receiver) Integrated A/V Receiver HDTV sets Car A/V Systems DVD Add-On Cards for High-End PCs Digital Audio Workstations Other Multi-Channel Digital Audio Systems
Functional Block Diagram
REC_SDO
REC Output
MBCK MLRCK MSDIN[0:2] SBCK[0:2] SLRCK[0:2] SSDIN[0:2]
REC_PWM_L+ REC_PWM_LREC_PWM_R+ REC_PWM_RPWM_CH1+ PWM_CH1-
Input Mux
Sample Rate Converter Mixer 4-Band EQ Tone Control Bass Manager Volume Control
PWM_CH2+ PWM_CH2-
MCLK MIC_BCK MIC_LRCK MIC_SDIN
PWM Modulator
PWM_CH3+ PWM_CH3PWM_CH4+ PWM_CH4PWM_CH5+ PWM_CH5PWM_CH6+ PWM_CH6-
Mic. Input Processor
Internal Clocks
Dynamic Range Compressor
SPI/I2C SO/SDA SCK/SCL SI/I2C_AD0 /CS/I2C_AD2 EXT_MUTE
I2C, SPI Interface
Internal Controls
PWM INVERT OVERLOAD
PLL
/RESET
CLK_IN
PLL_CPC
PLL_BYPASS
Copyright (c) 2000-2003, Pulsus Technologies Inc.
1
2003 REV1.2
PULSUS
Specifications
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage (VDD to VSS) Input Current, (Any pin except Supply) Output Current (/Pin) Input Voltage Storage Temperature Min VSS - 0.3 VSS - 0.5 -65 Max 4.0 10 30 +7.0 +150
PS9702B
Units V mA mA V C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage (VDD to VSS) Supply Current (VDD = 3.3V) Input Voltage Ambient Operating Temperature Min 3.0 VSS -0.5 -20 Typ 3.3 170 Max 3.6 5.5 +75 Units V mA V C
ELECTRICAL CHARACTERISTICS
Parameter Input Leakage Current (except Pull-up, Pull-down Input) High-Level Input Voltage (except Schmitt Input) Low-Level Input Voltage (except Schmitt Input) High-Level Input Voltage (Schmitt Input) Low-Level Input Voltage (Schmitt Input) High-Level Output Voltage (IO = 2mA) Low-Level Output Voltage (IO = 2mA) Pull-up Resistance Pull-down Resistance Input Capacitance (f = 1MHz, VDD = 0V) Output Capacitance (f = 1MHz, VDD = 0V) Min 2.0 1.39 0.9 VDD - 0.4 20 20 Typ 50 50 Max 30 0.8 2.06 1.46 0.4 100 100 10 10 Units A V V V V V V k k pF pF
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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2003 REV1.2
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Pin Assignment
PS9702B
PWM_INVERT
PWM_CH6+
PWM_CH5+
PWM_CH4+
PWM_CH3+
PWM_CH2+
PWM_CH1+
PWM_CH6-
PWM_CH5-
PWM_CH4-
PWM_CH3-
PWM_CH2-
PWM_CH1-
VDD
VDD
VDD
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
OVERLOAD VDD VSS SO/SDA SCK/SCL SI/I2C_AD0 /CS/I2C_AD2 SPI/I2C VDD VSS CLK_IN
76 77 78 79 80 81 82 83 84 85 86 87 88
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS REC_PWM_LREC_PWM_L+ VSS VDD REC_PWM_RREC_PWM_R+ VSS EXT_MUTE VSS VDD REC_SDO MCLK VSS MIC_LRCK MIC_BCK MIC_SDIN VSS VDD AD_GAIN1 AD_GAIN0 VSS SLRCK2 SBCK2 SSDIN2
VSS VDD PLL_BYPASS /RESET VSS SCAN_TEST SCAN_ENA RAM_TEST
89 90 91 92 93 94 95 96 97
IO_TSTEN VDD VSS
98 99 100
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 VDD
SSDIN0
MSDIN2
MSDIN1
PLL_XPD
PLL_EXT_LPF
MSDIN0
SSDIN1
MBCK
MLRCK
SBCK0
SLRCK0
SBCK1
PLL_CPC
PLL_DVDD
PLL_AVDD
SLRCK1
VDD
VSS
VSS
PLL_DVSS
PS9702B (100pin Plastic QFP, Top View)
Copyright (c) 2000-2003, Pulsus Technologies Inc.
PLL_AVSS
PLL_TEST
VSS
3
VSS
25
1
2
3
4
5
6
7
8
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2003 REV1.2
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Pin Descriptions
Name Pin NO. Type Power and Ground PLL_AVDD PLL_AVSS PLL_DVDD PLL_DVSS VDD 6 8 3 2 15, 24, 32, 40, 46, 51, 58, 65, 72, 77, 84, 90, 99 9, 16, 20, 25, 29, 33, 37, 41, 43, 47, 50, 52, 55, 59, 62, 66, 69, 73, 75, 78, 85, 89, 93, 100 Analog Power Analog Ground PLL Power PLL Ground Power Description
PS9702B
PLL analog power supply. 3.3V supply voltage. PLL analog ground. PLL peripheral digital power supply. 3.3V supply voltage. PLL digital ground. Digital power supply. 3.3V supply voltage.
VSS
Ground
Digital ground.
System Services /RESET 92 I H/W reset signal. Active Low Schmitt-Trigger input. The Schmitt-Trigger input allows a slowly rising input to reset the chip reliably. The RESET signal must be asserted `Low' during power up. De-assert `High' for normal operation. External clock input. 12.288MHz is recommended. When the PLL_BYPASS is "LOW", the external clock input from CLK_IN is used as PLL reference clock source. The external oscillator generates 12.288MHz clock and the internal PLL generates 98.304MHz (12.288MHz x 8) system clock. When the PLL_BYPASS is "HIGH", the PS9702B directly uses the CLK_IN signal (98.304MHz clock) as system clock. PLL bypass path selection input. Active High. Internal pull-down resistor. Internal PLL Power Down. Active Low. Don't pull down "PLL_XPD" pin when PWM output is activated. Internal pull-up resistor. Internal PLL Charge Pump Current Selection input. `LOW' for 100uA, `HIGH" for 50uA. Internal pull-down resistor. External PLL low pass filter pin.
CLK_IN
86
I
PLL_BYPASS PLL_XPD
91 4
I I
PLL_CPC
5
I
PLL_EXT_LPF
7
Analog
PCM Audio Input/Output Interface MBCK MLRCK MSDIN[0:2] SBCK[0:2] 13 14 12-10 18, 22, 27 I I I I/O PCM bit clock input of main six-channel audio. Schmitt-Trigger input. PCM Word clock (left-right clock) input of main six-channel audio. Schmitt-Trigger input. PCM serial data input of main six-channel audio. Schmitt-Trigger input. PCM bit clock input/output of sub-channel audio. User can select the master/slave mode of this signal. 4 2003 REV1.2
Copyright (c) 2000-2003, Pulsus Technologies Inc.
PULSUS
Name SLRCK[0:2] SSDIN[0:2] Pin NO. 19, 23, 28 17, 21, 26 Type I/O I Description
PS9702B
PCM Word clock (left-right clock) input/output of sub-channel audio. PCM serial data input of sub-channel audio. This sub-channel data can be treated as three two-channel audio or one six-channel audio. When it is used for six-channel audio, user can select the bit clock and word clock from SBCK[0:2] and SLRCK[0:2]. Main clock for external A/DC or D/AC. Clock frequency is 12.288MHz (fixed). PCM bit clock output of external MIC. Bit clock frequency is 3.072MHz (48KHz x 64, fixed) PCM Word clock (left-right clock) output of external MIC. Word clock rate is 48KHz (fixed). PCM serial data input of external MIC. Schmitt-Trigger input. PCM serial data output of record-out. This signal is synchronized to MIC_BCK and MIC_LRCK.
MCLK MIC_BCK MIC_LRCK MIC_SDIN REC_SDO
38 35 36 34 39
O O O I O
PWM Audio Output PWM_CH1+ PWM_CH1PWM_CH2+ PWM_CH2PWM_CH3+ PWM_CH3PWM_CH4+ PWM_CH4PWM_CH5+ PWM_CH5PWM_CH6+ PWM_CH6REC_PWM_R+ REC_PWM_RREC_PWM_L+ REC_PWM_L53 54 56 57 60 61 63 64 67 68 70 71 44 45 48 49 O O O O O O O O O O O O O O O O Positive PWM output of channel 1. (default setting : front left channel) Negative PWM output of channel 1. Positive PWM output of channel 2. (default setting : front right channel) Negative PWM output of channel 2. Positive PWM output of channel 3. (default setting : rear left channel) Negative PWM output of channel 3. Positive PWM output of channel 4. (default setting : rear right channel) Negative PWM output of channel 4. Positive PWM output of channel 5. (default setting : center channel) Negative PWM output of channel 5. Positive PWM output of channel 6. (default setting: sub-woofer channel) Negative PWM output of channel 6. Positive PWM output of Record-out left channel. Negative PWM output of Record-out left channel. Positive PWM output of Record-out right channel. Negative PWM output of Record-out right channel.
System Control Interface SPI/I2C 83 I Host interface mode (SPI or I2C) selector. Assert `HIGH' for SPI mode. De-assert `LOW' for I2C mode. Internal pull-down resistor. SO for SPI mode or SDA for I2C mode. SCK for SPI mode or SCL for I2C mode. Schmitt-Trigger input. 5 2003 REV1.2
SO/SDA SCK/SCL
79 80
I/O I
Copyright (c) 2000-2003, Pulsus Technologies Inc.
PULSUS
Name SI/I2C_AD0 Pin NO. 81 Type I Description
PS9702B
SI for SPI mode or Slave Address 0 for I2C mode. Schmitt-Trigger input. Internal pull-down resistor. Chip selector (CS) for SPI mode or Slave Address 2 for I2C mode. Schmitt-Trigger input. Internal pull-down resistor.
/CS/I2C_AD2
82
I
Special Control Interface EXT_MUTE 42 I External mute control input. Active High. Assert `HIGH' to mute the output. Internal pull-down resistor. Inverting control input of the PWM output. Active High. Assert `HIGH' to invert the PWM output. Default is non-inverting mode. Internal pull-down resistor. Power stage overload indication input. Polarity is programmable. Schmitt-Trigger input. When OVERLOAD is asserted, all PWM audio outputs go to "LOW" (if PWM_INVERT pin is `LOW"). Internal pull-down resistor. External A/D converter's gain control output. Test Mode PLL_TEST 1 I Internal PLL test mode. Active High. In normal operation, it should be "LOW" or not connected. Internal pull-down resistor. Scan test mode selector. Active High. In normal operation, it should be "LOW" or not connected. Internal pull-down resistor. Scan enable. Active High. In normal operation, it should be "LOW" or not connected. Internal pull-down resistor. Internal SRAM test mode. Active High. In normal operation, it should be "LOW" or not connected. Internal pull-down resistor. I/O Test pin. Active High. In normal operation, it should be "LOW" or not connected. Internal pull-down resistor. Not connected pin. This pin should not be connected to any other signal.
PWM_INVERT
74
I
OVERLOAD
76
I
AD_GAIN[0:1]
30, 31
O
SCAN_TEST
94
I
SCAN_ENA
95
I
RAM_TEST
96
I
IO_TSTEN
98
I
NC
87, 88, 97
All inputs and bi-directional inputs are 5 Volt tolerant. The corresponding pins can be connected to the buses that can swing between 0V and 5V. The output-only pins are not 5V tolerant and the buses they are connected to can swing only between 0V and 3.3V.
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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2003 REV1.2
PULSUS
Signal Interface Diagram
PS9702B
CLK_IN
PWM_CH[1..6]+
PWM Output
PWM_CH[1..6]PWM_INVERT OVERLOAD
Clock & PLL
PLL_CPC PLL_BYPASS
MBCK
Main Audio Interface
MLRCK MSDIN[0:2]
REC_SDO REC_PWM_RREC_PWM_R+
Record Output Interface
SBCK[0:2]
REC_PWM_LREC_PWM_L+
Sub Audio Interface
SLRCK[0:2] SSDIN[0:2] AD_GAIN[0:1]
/RESET PLL_XPD
MCLK
SCAN_TEST SCAN_ENA RAM_TEST PLL_TEST IOTST_EN VDD
Mic Input Interface
MIC_BCK MIC_LRCK MIC_SDIN
EXT_MUTE
Global Interface (Reset, Test & Power)
SPI/I2C
PLL_DVDD PLL_AVDD VSS PLL_DVSS PLL_AVSS
Serial Control Interface (SPI or I2C)
SO/SDA SCK/SCL SI/I2C_AD0 /CS/I2C_AD2
PS9702B
Copyright (c) 2000-2003, Pulsus Technologies Inc.
7
2003 REV1.2
PULSUS
Signal Descriptions
1. Clock and Reset
PS9702B
The PS9702B uses 98.304MHz (48KHz x 2048) system clock internally. The PS9702B uses external 12.288MHz clock source and has x8 PLL (Phase Locked Loop) for internal system clock generation. PS9702B can select the system clock between the internally generated clock and the external input clock (In this case the external input clock must be 98.304MHz).
2. PCM Audio Input Signals
PS9702B uses serial interface for PCM audio data input using BCK, LRCK, and DIN pins. It has one input port for six channel audio data (named as main channel) and has three sub-input port for two channel audio data (named as sub-channel). But the three sub-input ports can be used as one six-channel audio input port.
3. PWM Audio Output Signals
The PS9702B converts PCM audio data to PWM audio signal. It outputs one six-channel PWM signal for main audio, one two-channel PWM signal for record-out and one additional two-channel PCM signal for record-out. All PWM signal consist of the both positive and negative PWM signals.
4. Control Interface Signals
The PS9702B supports internal control register I/O using both SPI and I C. The pin SPI/I2C selects the control interface method. The control registers has 8-bit address space and 16-bit or 24-bit data length. All internal control registers are both readable and writable.
2
5. Special Control Signals
The PS9702B can generate only AD mode PWM signal. For more information about the Power stage driving method and BD/AD mode of PWM amplifier, refer the "PULSUS PWM Amplification application notes". The PS9702B has Overload protection logic. When the pin OVERLOAD is "HIGH" (default setting, the polarity is programmable), the PS9702B goes to protection mode and all PWM outputs go to "LOW" (default setting).
Copyright (c) 2000-2003, Pulsus Technologies Inc.
8
2003 REV1.2
PULSUS
Control Interface Protocol
PS9702B
1. I2C Control Interface
The pin SPI/I2C selects the control interface method. When the pin SPI/I2C is grounded, the control 2 interface method is I C interface. The I C slave address can be varied using two I C slave address setting pin, I2C_AD0 and I2C_AD2. The base slave address is 0x38 with I2C_AD0 and I2C_AD2 pin grounded. Figure below shows you the configuration of slave address.
2 2
I2C_AD2 I2C_AD0 SDA SCL
Slave Address (7 bit) Start Condition R/W ACK 0 1 1 1 AD2 0 AD0
I2C_AD2 0 0 1 1
I2C_AD0 0 1 0 1
PS9702B Slave Address 0x38 (0b0111000) 0x39 (0b0111001) 0x3C (0b0111100) 0x3D (0b0111101)
The control registers has 8-bit address space and 16-bit or 24-bit data length. If the upper two bits of register address are all HIGH, 11xx xxxx, then the data length will be three bytes (24 bits). The other case, the data length will be two bytes (16 bits). The I C control protocol diagram is in the next page.
2
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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2003 REV1.2
PULSUS
2Bytes Write Operation (I2C interface)
PS9702B
SDA SCL
7-1 Start Condition PS9702B Slave Address W : Write R : Read ACK : Acknowledge 8 W 9 ACK
00xx xxxx
8-1 Register Address to write ACK
16-9 DATA ACK
8-1 DATA ACK Stop Condition
3Bytes Write Operation (I2C interface)
SDA SCL
7-1 Start Condition PS9702B Slave Address W : Write R : Read ACK : Acknowledge 8 W 9 ACK
11xx xxxx
8-1 Register Address to write ACK
24-17 DATA ACK
16-9 DATA ACK
8-1 DATA ACK Stop Condition
2Bytes Read Operation (I2C interface)
SDA SCL
7-1 PS9702B Slave Address 8 W 9 ACK
00xx xxxx
8-1 Register Address to read ACK Stop Condition
7-1 PS9702B Slave Address Start Condition
8 R ACK
16-9 DATA ACK
8-1 DATA ACK Stop Condition
Start Condition
W : Write R : Read ACK : Acknowledge
3Bytes Read Operation (I2C interface)
SDA SCL
7-1 PS9702B Slave Address W : Write R : Read ACK : Acknowledge 8 W 9 ACK
11xx xxxx
8-1 Register Address to read ACK Stop Condition
7-1 PS9702B Slave Address Start Condition
8 R ACK
24-17 DATA ACK
16-9 DATA ACK
8-1 DATA ACK Stop Condition
Start Condition
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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2003 REV1.2
PULSUS
2. SPI Control Interface
PS9702B
The pin SPI/I2C selects the control interface method. When the pin SPI/I2C is connected to VCC, the control interface method is SPI interface. SPI control protocol diagram is below.
Write Operation (SPI interface)
/CS SCK SI SO
W/R Register Address Data [24:1] or Data [16:1] 8-1 24 ( or 16 ) - 1
Read Operation (SPI interface)
/CS SCK SI SO
W/R Register Address 8-1 24 ( or 16 ) - 1 Data [24:1] or Data [16:1]
Copyright (c) 2000-2003, Pulsus Technologies Inc.
11
2003 REV1.2
PULSUS
Control Register Descriptions
PS9702B
Register Name
Address
Word Length DDC Soft Reset Register
Description
DDC_RESET
0x00
2 Bytes
PWM output activation control register. [0]: PWM modulator Reset control. Default = "1". "0" = PWM On "1" = PWM Off [3:1]: Reserved. [4]: SRC (Sample Rate Converter) Lock indication. Active High. Read only. "0" = Unlock (or No signal) "1" = Lock [8:5]: Input sample rate indication. Read only. "0001" = 32KHz "0010" = 44.1KHz "0011" = 48KHz "0110" = 88.2KHz "0111" = 96KHz "1010" = 176.4KHz "1011" = 192KHz [15:9]: Not Used.
Default = 0x0XX1
Input Interface Unit Configuration Registers
IN_CONTROL
0x01
2 Bytes
Serial data input interface control register. [1:0]: BCK count. Default = "10". "00" = 16bit, "01" = 24bit, "10" = 32bit. [2]: BCK polarity. Default = "1". "0" = Valid data at Negative edge "1" = Valid data at Positive edge [3]: Data align. "0" = Right aligned, "1" = Left aligned. Default = "1". [4]: LRCK left high. Default = "0". "0" = Right data when LRCK is high. "1" = Left data when LRCK is high. [5]: Data MSB first. "0" = LSB first, "1" = MSB first. Default = "1". [7:6]: Data word length. Default = "11". "00" = 16bit, [15:9]: Not Used.
Default = 0x01EE
"01" = 18bit,
"10" = 20bit,
"11" = 24bit.
[8]: I2S compatible. "1" = Compatible. Default = "1".
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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2003 REV1.2
PULSUS
Register Name Address Word Length Description
PS9702B
MIC_CONTROL
0x02
2 Bytes
MIC data input interface control register. This register is not changable and is fixed to default value. [8:0]: BCK count. Default = "10". "00" = 16bit, "10" = 32bit. [2]: BCK polarity. Default = "1". "0" = Valid data at Negative edge. "1" = Valid data at Positive edge. [3]: Data align. "0" = Right aligned. "1" = Left aligned. Default = "1". [4]: LRCK left high. Default = "0". "0" = Right data when LRCK is high. "1" = Left data when LRCK is high. [5]: Data MSB first. "0" = LSB first, "1" = MSB first. Default = "1". [7:6]: Data word length. Default = "11". "00" = 16bit, [15:9]: Not Used.
Default = 0x01EE
"01" = 18bit,
"10" = 20bit, "11" = 24bit.
[8]: I2S compatible. "1" = Compatible. Default = "1".
CHANNEL_CONFIGURE
0x03
2 Bytes
Register for serial input data port configuration. [2:0]: I2S Input port selector. Default = "100". "000" = Sub two-channel input mode using SDIN[0], SBCK[0], and SLRCK[0]. "001" = Sub two-channel input mode using SDIN[1], SBCK[1], and SLRCK[1]. "01x" = Sub two-channel input mode using SDIN[2], SBCK[2], and SLRCK[2]. "100" = Main six-channel input mode using MBCK and MLRCK. "101" = Sub six-channel input using SBCK[0] and SLRCK[0]. "110" = Sub six-channel input using SBCK[1] and SLRCK[1]. "111" = Sub six-channel input using SBCK[2] and SLRCK[2]. [4:3]: Reserved. [5]: Master-slave mode selector for SBCK[0] and SLRCK[0]. Default = "0". "0" = Slave mode, "0" = Slave mode, "0" = Slave mode, "1" = Master mode. "1" = Master mode. "1" = Master mode. [6]: Master-slave mode selector for SBCK[1] and SLRCK[1]. Default = "0". [7]: Master-slave mode selector for SBCK[2] and SLRCK[2]. Default = "0". [8]: I2S/SPDIF input selector. PS9702B can receive the both I2S and SPDIF input. "0" means the input is SPDIF input. "1" means the input is I2S input. Default = "1". [10:9]: SPDIF input port selector. Default = "00". "00" = SPDIF input from SDATA[0]. "01" = SPDIF input from SBCK[0]. "10" = SPDIF input from SLRCK[0]. "11" = SPDIF input from SDATA[0]. [15:11]: Not Used.
Default = 0x0104
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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Register Name Address Word Length Volume Configuration Registers Description
PS9702B
VOLUME1_CONTROL
0x05
2 Bytes
The PS9702B supports digital volume gain control with the resolution of 0.5dB/step. The maximum volume gain is +24dB and the minimum volume gain (except -dB) is -70dB. The each volume control register has 8-bit resolution. The register value 0x00 means +24dB, and the value 0xBC means -70dB. And the register value larger than 0xBC means sound mute. Table A-1 shows the relations between the register value and volume gain. [15:8]: PWM output Channel 1 volume. [7:0]: PWM output Channel 2 volume.
Default = 0xBDBD (Mute)
VOLUME2_CONTROL
0x06
2 Bytes
Table A-1 shows the relations between the register value and volume gain. [15:8]: PWM output Channel 3 volume. [7:0]: PWM output Channel 4 volume.
Default = 0xBDBD (Mute)
VOLUME3_CONTROL
0x07
2 Bytes
Table A-1 shows the relations between the register value and volume gain. [15:8]: PWM output Channel 5 volume. [7:0]: PWM output Channel 6 volume.
Default = 0xBDBD (Mute)
VOLUME4_CONTROL
0x08
2 Bytes
Table A-1 shows the relations between the register value and volume gain. [15:8]: Record out left volume. [7:0]: Record out right volume.
Default = 0x3030 (0dB)
Dynamic Range Compressor Configuration Registers
THRESHOLD1_CONTROL
0x09
2 Bytes
Automatic gain control (AGC) threshold level. The AGC threshold level is controlled in dB magnitude and it has 0.5dB/step resolution. This register has 8-bit resolution and has the same meaning of volume control register. Table A-1 shows the relations between the register value and threshold level. [15:8]: AGC threshold of PWM output Channel 1 and Channel 2. [7:0]: Reserved.
Default = 0x3131 (-0.5dB)
THRESHOLD2_CONTROL
0x0A
2 Bytes
Table A-1 shows the relations between the register value and threshold level. [15:8]: AGC threshold of PWM output Channel 3. [7:0]: AGC threshold of PWM output Channel 4.
Default = 0x3131 (-0.5dB)
THRESHOLD3_CONTROL
0x0B
2 Bytes
Table A-1 shows the relations between the register value and threshold level. [15:8]: AGC threshold of PWM output Channel 5. [7:0]: AGC threshold of PWM output Channel 6.
Default = 0x3131 (-0.5dB)
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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Register Name Address Word Length Description
PS9702B
AGC_CONTROL
0x11
2 Bytes
AGC control register. [3:0]: AGC attack length control value. Default = 0x6. [6:4]: AGC attack height (in 0.5dB scale). Default = 0x3. [15:7]: AGC release length (x 0.6667msec). Default = 0x180 (0.256 sec).
Default = 0xC036
PWM Modulator Configuration Register
PWM_CONTROL1
0x13
2 Bytes
PWM modulator control register 1. [0]: Modulation index(PCM to PWM gain). Default = "0". "0" = 90.63% "1" = 93.75% [1]: Auto DC cut enable. Active high. Default = "1". [5:2]: Reserved. Default = "0000" [6]: Overload input signal polarity. Default = "1" "0" = Active Low, "1" = Active High. [11:7]: Overload sustained time. When overload condition is detected, all PWM outputs go to shutdown during assigned time.
Default = "10000" (2.73sec)
"00000" = No shutdown. "00001" ~ "11110" = multiple of 0.17sec. "11111" = No recovery. To recover PWM signal, set the DDC_RESET register (0x00) to "1" (PWM off) and then "0" (PWM on). [15:12]: Reserved.
Default = 0x0842
PWM_CONTROL2
0x14
2 Bytes
PWM modulator control register 2. [0]: Interpolation method. "0" = Soft, "1" = Sharp. Default = "0". [1]: Dither enable. "0" = Dither disable, "1" = Dither enable. Default = "0". [2]: High S/N mode enable. "0" = Normal mode, "1" = High S/N mode. Default = "0". [3]: High bandwidth Noise shaping filter enable. Default = "0". "0" = Normal mode. "1'" = High bandwidth N/S filter enable. [7:4]: PWM Linearizer Coefficient. Default = "0000". [9:8]: Switching Frequency. Default = "00". "00", "11" = 384KHz "01" = 192KHz "10" = 96KHz. [11:10]: Dead time between positive and negative PWM signal. The unit is PWM clock (98.304MHz). Default = "00". [14:12]: Modulation limit. The unit is PWM clock (98.304MHz). Default = "000". [15]: Reserved.
Default = 0x0000
Copyright (c) 2000-2003, Pulsus Technologies Inc.
15
2003 REV1.2
PULSUS
Register Name Address Word Length Status Monitoring Register Description
PS9702B
SPDIF_CONTROL
0x17
2 Bytes
SPDIF status register. [4:0]: Reserved. Default = "00111" [14:5]: SPDIF input status report register. Read only. [5]: Pre-Emphasis flag. "0" = No emphasis, "1" = Emphasis. [6]: Professional format flag. "0" = Consumer, "1" = Professional. [7]: Copy enable flag. "0" = Copy inhibit, "1" = Copy enable. [8]: Non-audio flag. "0" = Audio, "1" = Non-audio. [9]: SPDIF detected flag. "1" means the PS9702B detects the SPDIF sync-word. [10]: Parity error flag. "0" = Non error, "1" = Error. [11]: Max word length 24 flag. "0" = Max 20-bit, "1" = Max 24-bit. [14:12]: Word length. Max 24 000 001 010 011 100 101 Others [15]: Not Used.
Default = 0x0007
0 Default 19 18 17 16 20 Reserved
1 Default 23 22 21 20 24 Reserved
OVERLOAD_STATE
0x18
2 Bytes
Overload status monitoring register. [0]: Overload status. Read only. "0" = Overload protection is not detected or output protection is ended. "1" = Overload is detected and output protection is working. [15:1]: Not Used.
Default = 0x0000
Muting Control Register
SYS_SOFT_MUTE
0x3C
2 Bytes
System mute control register. [0]: Mute. Active high. Default = "1" [1]: Soft mute function enable. Active high. Default = "1" [2]: Internal system mute monitoring bit. Read only. [10:3]: Internal soft mute level counter. Read only. [15:11]: Reserved.
Default = 0x0XX7
Copyright (c) 2000-2003, Pulsus Technologies Inc.
16
2003 REV1.2
PULSUS
Register Name Address Word Length MIC Mixer Configuration Register Description
PS9702B
MIC_MIX_LEVEL
0x81
2 Bytes
Mixing level of two microphone input. The each mixing level value consists of mixing polarity (1-bit) and mixing level coefficient (7-bit). MSB is the mixing polarity ("0" : +, "1" : -) and LS 7-bit is the mixing level coefficient. Table A-2 shows the relations between the register value and mixing level. [7..0]: MIC0 input into Mic mixer output mixing level. [15..8]: MIC1 input into Mic mixer output mixing level.
Default = 0x3030. (-6dB)
De-Emphasis Control Register
DE_EMPHASIS
0x82
2 Bytes
De-Emphasis control Register. [0]: De-Emphasis control of Front two channel. Active high. [15:1]: Not Used.
Default = 0x0000
Input Channel Mapping Configuration Registers
INPUT_CH_MAPPING1
0x83
2 Bytes
Input channel Mapping Register1. "0" : Input Channel 0 (left channel data from SDIN0) "1" : Input Channel 1 (right channel data from SDIN0) "2" : Input Channel 2 (left channel data from SDIN1) "3" : Input Channel 3 (right channel data from SDIN1) "4" : Input Channel 4 (left channel data from SDIN2) "5" : Input Channel 5 (right channel data from SDIN2) "6", "7" : not used [2:0]: Input Channel number that is linked to Left Channel. [3]: Not Used. [6:4]: Input Channel number that is linked to Right Channel. [15:7]: Not Used.
Default = 0x0010
INPUT_CH_MAPPING2
0x84
2 Bytes
Input channel Mapping Register2. [2:0]: Input Channel number that is linked to Left Surround Channel. [3]: Not Used. [6:4]: Input Channel number that is linked to Right Surround Channel. [7]: Not Used. [10:8]: Input Channel number that is linked to LFE Channel. [11]: Not Used. [14:12]: Input Channel number that is linked to Center Channel. [15]: Not Used.
Default = 0x5432
Copyright (c) 2000-2003, Pulsus Technologies Inc.
17
2003 REV1.2
PULSUS
Register Name Address Word Length Mixer Configuration Registers Description
PS9702B
LR2L_MIX_LEVEL
0x85
2 Bytes
Left and Right into Left Mixing level register. The each mixing level register consists of mixing polarity (1-bit) and mixing level coefficient (7-bit). MSB is the mixing polarity ("0" : +, "1" : -) and LS 7-bit is the mixing level coefficient. Table A-2 shows the relations between the register value and mixing level. [7..0]: Left channel input into Left channel output mixing level. [15..8]: Right channel input into Left channel output mixing level.
Default = 0xFF24 (Mute, (+)0dB)
CM2L_MIX_LEVEL
0x86
2 Bytes
Center and MIC into Left Mixing level register. [7..0]: Center channel input into Left channel output mixing level. [15..8]: MIC input into Left channel output mixing level.
Default = 0xFFFF (Mute, Mute)
RL2R_MIX_LEVEL
0x87
2 Bytes
Right and Left into Right Mixing level register. [7..0]: Right channel input into Right channel output mixing level. [15..8]: Left channel input into Right channel output mixing level.
Default = 0xFF24 (Mute, (+)0dB)
CM2R_MIX_LEVEL
0x88
2 Bytes
Center and MIC into Right Mixing level register. [7..0]: Center channel input into Right channel output mixing level. [15..8]: MIC input into Right channel output mixing level.
Default = 0xFFFF (Mute, Mute)
LSL2LS_MIX_LEVEL
0x89
2 Bytes
Left Surround and Left into Left Surround Mixing level register. [7..0]: Left Surround channel input into Left Surround channel output mixing level. [15..8]: Left channel input into Left Surround channel output mixing level.
Default = 0xFF24 (Mute, (+)0dB)
RM2LS_MIX_LEVEL
0x8a
2 Bytes
Right and MIC into Left Surround Mixing level register. [7..0]: Right channel input into Left Surround channel output mixing level. [15..8]: MIC input into Left Surround channel output mixing level.
Default = 0xFFFF (Mute, Mute)
RSL2RS_MIX_LEVEL
0x8b
2 Bytes
Right Surround and Left into Right Surround Mixing level register. [7..0]: Right Surround channel input into Right Surround channel output mixing level. [15..8]: Left channel input into Right Surround channel output mixing level.
Default = 0xFF24 (Mute, (+)0dB)
RM2RS_MIX_LEVEL
0x8c
2 Bytes
Right and MIC into Right Surround Mixing level register. [7..0]: Right channel input into Right Surround channel output mixing level. [15..8]: MIC input into Right Surround channel output mixing level.
Default = 0xFFFF (Mute, Mute)
Copyright (c) 2000-2003, Pulsus Technologies Inc.
18
2003 REV1.2
PULSUS
Register Name Address Word Length Description
PS9702B
CL2C_MIX_LEVEL
0x8d
2 Bytes
Center and Left into Center Mixing level register. [7..0]: Center channel input into Center channel output mixing level. [15..8]: Left channel input into Center channel output mixing level.
Default = 0xFF24 (Mute, (+)0dB)
RM2C_MIX_LEVEL
0x8e
2 Bytes
Right and MIC into Center Mixing level register. [7..0]: Right channel input into Center channel output mixing level. [15..8]: MIC input into Center channel output mixing level.
Default = 0xFFFF (Mute, Mute)
Equalizer Configuration Registers
EQ_SEL_ENA
0x8F
2 Bytes
Equalizer configuration Register. [0]: Left channel Equalizer Enable. Active high. Default = "0" (Disable) [1]: Right channel Equalizer Enable. Active high. Default = "0" (Disable) [2]: Left surround channel Equalizer Enable. Active high. Default = "0" (Disable) [3]: Right surround channel Equalizer Enable. Active high. Default = "0" (Disable) [4]: Center channel Equalizer Enable. Active high. Default = "0" (Disable) [7..5]: Not Used. [8]: Left channel Equalizer Select. "0" for Primary filter set and "1" for Secondary filter set. Default = "0" (Primary filter) [9]: Right channel Equalizer Select. Default = "0" (Primary filter) [10]: Left surround channel Equalizer Select. Default = "0" (Primary filter) [11]: Right surround channel Equalizer Select. Default = "0" (Primary filter) [12]: Center channel Equalizer Select. Default = "0" (Primary filter) [15..13]: Not Used.
Default = 0x0000
EQ_L01_LEVEL
0x90
2 Bytes
Left channel Equalizer 0, 1 level register. -15dB to 15dB in 1dB/step resolution. Table A-3 shows the relations between the register value and Equalizer level. [4..0]: Left channel Equalizer 0 level. [7..5]: Not Used. [12..8]: Left channel Equalizer 1 level. [15..13]: Not Used.
Default = 0x0000 (0dB, 0dB)
EQ_L23_LEVEL
0x91
2 Bytes
Left channel Equalizer 2, 3 level register. Table A-3 shows the relations between the register value and Equalizer level. [4..0]: Left channel Equalizer 2 level. [7..5]: Not Used. [12..8]: Left channel Equalizer 3 level. [15..13]: Not Used.
Default = 0x0000 (0dB, 0dB)
Copyright (c) 2000-2003, Pulsus Technologies Inc.
19
2003 REV1.2
PULSUS
Register Name Address Word Length Description
PS9702B
EQ_R01_LEVEL
0x92
2 Bytes
Right channel Equalizer 0, 1 level register. Table A-3 shows the relations between the register value and Equalizer level. [4..0]: Right channel Equalizer 0 level. [7..5]: Not Used. [12..8]: Right channel Equalizer 1 level. [15..13]: Not Used.
Default = 0x0000 (0dB, 0dB)
EQ_R23_LEVEL
0x93
2 Bytes
Right channel Equalizer 2, 3 level register. Table A-3 shows the relations between the register value and Equalizer level. [4..0]: Right channel Equalizer 2 level. [7..5]: Not Used. [12..8]: Right channel Equalizer 3 level. [15..13]: Not Used.
Default = 0x0000 (0dB, 0dB)
EQ_LS01_LEVEL
0x94
2 Bytes
Left surround channel Equalizer 0, 1 level register. Table A-3 shows the relations between the register value and Equalizer level. [4..0]: Left surround channel Equalizer 0 level. [7..5]: Not Used. [12..8]: Left surround channel Equalizer 1 level. [15..13]: Not Used.
Default = 0x0000 (0dB, 0dB)
EQ_LS23_LEVEL
0x95
2 Bytes
Left surround channel Equalizer 2, 3 level register. Table A-3 shows the relations between the register value and Equalizer level. [4..0]: Left surround channel Equalizer 2 level. [7..5]: Not Used. [12..8]: Left surround channel Equalizer 3 level. [15..13]: Not Used.
Default = 0x0000 (0dB, 0dB)
EQ_RS01_LEVEL
0x96
2 Bytes
Right surround channel Equalizer 0, 1 level register. Table A-3 shows the relations between the register value and Equalizer level. [4..0]: Right surround channel Equalizer 0 level. [7..5]: Not Used. [12..8]: Right surround channel Equalizer 1 level. [15..13]: Not Used.
Default = 0x0000 (0dB, 0dB)
EQ_RS23_LEVEL
0x97
2 Bytes
Right surround channel Equalizer 2, 3 level register. Table A-3 shows the relations between the register value and Equalizer level. [4..0]: Right surround channel Equalizer 2 level. [7..5]: Not Used. [12..8]: Right surround channel Equalizer 3 level. [15..13]: Not Used.
Default = 0x0000 (0dB, 0dB)
Copyright (c) 2000-2003, Pulsus Technologies Inc.
20
2003 REV1.2
PULSUS
Register Name Address Word Length Description
PS9702B
EQ_C01_LEVEL
0x98
2 Bytes
Center channel Equalizer 0, 1 level register. Table A-3 shows the relations between the register value and Equalizer level. [4..0]: Center channel Equalizer 0 level. [7..5]: Not Used. [12..8]: Center channel Equalizer 1 level. [15..13]: Not Used.
Default = 0x0000 (0dB, 0dB)
EQ_C23_LEVEL
0x99
2 Bytes
Center channel Equalizer 2, 3 level register. Table A-3 shows the relations between the register value and Equalizer level. [4..0]: Center channel Equalizer 2 level. [7..5]: Not Used. [12..8]: Center channel Equalizer 3 level. [15..13]: Not Used.
Default = 0x0000 (0dB, 0dB)
EQ_MODE
0x9A
2 Bytes
Equalizer operation mode setting register. "0"=Parallel operation (Graphic EQ mode). In this mode, EQ level is effective. "1"=Cascade operation (Parametric EQ mode). In this mode, EQ level is ineffective. [0]: Primary Equalizer filter set operation mode. [1]: Secondary Equalizer filter set operation mode. [15..2]: Not Used.
Default = 0x0000 (Parallel, Parallel)
EQ_P_SHIFT01
0x9B
2 Bytes
Primary Equalizer filter 0, 1 shifting value for scaling. [4..0]: Primary Equalizer 0 shifting value. [7..5]: Not Used. [12..8]: Primary Equalizer 1 shifting value. [15..13]: Not Used.
Default = 0x0B07 (11, 7)
EQ_P_SHIFT23
0x9C
2 Bytes
Primary Equalizer filter 2, 3 shifting value for scaling. [4..0]: Primary Equalizer 2 shifting value. [7..5]: Not Used. [12..8]: Primary Equalizer 3 shifting value. [15..13]: Not Used.
Default = 0x120F (18, 15)
EQ_S_SHIFT01
0x9D
2 Bytes
Secondary Equalizer filter 0, 1 shifting value for scaling. [4..0]: Secondary Equalizer 0 shifting value. [7..5]: Not Used. [12..8]: Secondary Equalizer 1 shifting value. [15..13]: Not Used.
Default = 0x0000 (0, 0)
Copyright (c) 2000-2003, Pulsus Technologies Inc.
21
2003 REV1.2
PULSUS
Register Name Address Word Length Description
PS9702B
EQ_S_SHIFT23
0x9E
2 Bytes
Secondary Equalizer filter 2, 3 shifting value for scaling. [4..0]: Secondary Equalizer 2 shifting value. [7..5]: Not Used. [12..8]: Secondary Equalizer 3 shifting value. [15..13]: Not Used.
Default = 0x0000 (0, 0) Tone Control Registers
TB_L_LEVEL
0x9F
2 Bytes
Left channel Bass, Treble level register. -15dB to 15dB in 1dB/step resolution. Table A-3 shows the relations between the register value and tone control level. [4..0]: Left channel Bass level. [7..5]: Not Used. [12..8]: Left channel Treble level. [15..13]: Not Used.
Default = 0x0000 (0dB, 0dB)
TB_R_LEVEL
0xA0
2 Bytes
Right channel Bass, Treble level register. Table A-3 shows the relations between the register value and tone control level. [4..0]: Right channel Bass level. [7..5]: Not Used. [12..8]: Right channel Treble level. [15..13]: Not Used.
Default = 0x0000 (0dB, 0dB)
TB_LS_LEVEL
0xA1
2 Bytes
Left Surround channel Bass, Treble level register. Table A-3 shows the relations between the register value and tone control level. [4..0]: Left Surround channel Bass level. [7..5]: Not Used. [12..8]: Left Surround channel Treble level. [15..13]: Not Used.
Default = 0x0000 (0dB, 0dB)
TB_RS_LEVEL
0xA2
2 Bytes
Right Surround channel Bass, Treble level register. Table A-3 shows the relations between the register value and tone control level. [4..0]: Right Surround channel Bass level. [7..5]: Not Used. [12..8]: Right Surround channel Treble level. [15..13]: Not Used.
Default = 0x0000 (0dB, 0dB)
TB_C_LEVEL
0xA3
2 Bytes
Center channel Bass, Treble level register. Table A-3 shows the relations between the register value and tone control level. [4..0]: Center channel Bass level. [7..5]: Not Used. [12..8]: Center channel Treble level. [15..13]: Not Used.
Default = 0x0000 (0dB, 0dB)
Copyright (c) 2000-2003, Pulsus Technologies Inc.
22
2003 REV1.2
PULSUS
Register Name Address Word Length Description
PS9702B
TB_FILTER_SHIFT
0xA4
2 Bytes
Treble, Bass filter shifting value for scaling. [4..0]: Bass filter shifting value. [7..5]: Not Used. [12..8]: Treble filter shifting value. [15..13]: Not Used.
Default = 0x120D (18, 13)
Bass Management Configuration Registers
BM_PATH_SELECT
0xA5
2 Bytes
Bass Management path control Register [0]: Subwoofer output path selection control. "0"=Bass Sum is sent to Subwoofer output. "1"=LFE channel is sent to Subwoofer output.
Default = "0" (Bass Sum to Subwoofer).
[1]: Bass Sum low-pass filter bypass control. Default = "0" (Filter Enable). "0"=Filter Enable "1"=Bypass (Filter Disable). [2]: Bass Sum low-pass filter order. Default = "0" (4th order). "0"=4th order "1"=2nd order. [7..3]: Not Used. [8]: Left channel bass management low-cut filter enable control. Active high. "0"=Disable. "1"=Enable. Default = "0" (Filter Disable). [9]: Right channel bass management low-cut filter control. Active high. "0"=Disable. "1"=Enable. Default = "0" (Filter Disable). [10]: Left surround channel bass management low-cut filter control. Active high. "0"=Disable. "1"=Enable. Default = "0" (Filter Disable). [11]: Right surround channel bass management low-cut filter control. Active high. "0"=Disable. "1"=Enable. Default = "0" (Filter Disable). [12]: Center channel bass management low-cut filter control. Active high. "0"=Disable. "1"=Enable. Default = "0" (Filter Disable). [15..13]: Not Used.
Default = 0x0000
BM_LR2SUM_LEVEL
0xA6
2 Bytes
Left and Right channel into Bass Sum mixing level register. The each mixing level register consists of mixing polarity (1-bit) and mixing level coefficient (7-bit). MSB is the mixing polarity ("0" : +, "1" : -) and LS 7-bit is the mixing level coefficient. Table A-2 shows the relations between the register value and mixing level. [7..0]: Left channel input into Bass Sum mixing level. [15..8]: Right channel input into Bass Sum mixing level.
Default = 0x4242 ((+) -15dB, (+) -15dB)
BM_LSRS2SUM_LEVEL
0xA7
2 Bytes
Left surround and Right surround channel into Bass Sum mixing level register. Table A-2 shows the relations between the register value and mixing level. [7..0]: Left surround channel input into Bass Sum mixing level. [15..8]: Right surround channel input into Bass Sum mixing level.
Default = 0x4242 ((+) -15dB, (+) -15dB)
Copyright (c) 2000-2003, Pulsus Technologies Inc.
23
2003 REV1.2
PULSUS
Register Name Address Word Length Description
PS9702B
BM_CLFE2SUM_LEVEL
0xA8
2 Bytes
Center and LFE channel into Bass Sum mixing level register. Table A-2 shows the relations between the register value and mixing level. [7..0]: Center channel input into Bass Sum mixing level. [15..8]: LFE channel input into Bass Sum mixing level.
Default = 0x2E42 ((+) -5dB, (+) -15dB)
BM_LFE_BYPASS_LEVEL
0xA9
2 Bytes
LFE into Subwoofer output bypass level register. This is effective when LFE channel input is bypassed to Subwoofer output. Table A-2 shows the relations between the register value and bypass level. [7..0]: LFE into Subwoofer output bypass level. [15..8]: Not Used.
Default = 0x0024 ((+) 0dB)
BM_L2L_LEVEL
0xAA
2 Bytes
Left channel input into Left channel pass-through mixing level register. Table A-2 shows the relations between the register value and mixing level. [7..0]: Left channel input into Left channel pass-through mixing level. [15..8]: Not Used.
Default = 0x0024 ((+) 0dB)
BM_LFESUM2L_LEVEL
0xAB
2 Bytes
LFE channel and Bass Sum into Left channel output mixing level register. Table A-2 shows the relations between the register value and mixing level. [7..0]: LFE channel input into Left channel output mixing level. [15..8]: Bass Sum into Left channel output mixing level.
Default = 0xFFFF (Mute, Mute)
BM_R2R_LEVEL
0xAC
2 Bytes
Right channel input into Right channel pass-through mixing level register. Table A-2 shows the relations between the register value and mixing level. [7..0]: Right channel input into Right channel pass-through mixing level. [15..8]: Not Used.
Default = 0x0024 ((+) 0dB)
BM_LFESUM2R_LEVEL
0xAD
2 Bytes
LFE channel and Bass Sum into Right channel output mixing level register. Table A-2 shows the relations between the register value and mixing level. [7..0]: LFE channel input into Right channel output mixing level. [15..8]: Bass Sum into Right channel output mixing level.
Default = 0xFFFF (Mute, Mute)
BM_LS2LS_LEVEL
0xAE
2 Bytes
Left surround channel input into Left surround channel pass-through mixing level register. Table A-2 shows the relations between the register value and mixing level. [7..0]: Left surround channel input into Left surround channel pass-through mixing level. [15..8]: Not Used.
Default = 0x0024 ((+) 0dB)
Copyright (c) 2000-2003, Pulsus Technologies Inc.
24
2003 REV1.2
PULSUS
Register Name Address Word Length Description
PS9702B
BM_LFESUM2LS_LEVEL
0xAF
2 Bytes
LFE channel and Bass Sum into Left surround channel output mixing level register. Table A-2 shows the relations between the register value and mixing level. [7..0]: LFE channel input into Left surround channel output mixing level. [15..8]: Bass Sum into Left surround channel output mixing level.
Default = 0xFFFF (Mute, Mute)
BM_RS2RS_LEVEL
0xB0
2 Bytes
Right surround channel input into Right surround channel pass-through mixing level register. Table A-2 shows the relations between the register value and mixing level. [7..0]: Right surround channel input into Right surround channel pass-through mixing level. [15..8]: Not Used.
Default = 0x0024 ((+) 0dB)
BM_LFESUM2RS_LEVEL
0xB1
2 Bytes
LFE channel and Bass Sum into Right surround channel output mixing level register. Table A-2 shows the relations between the register value and mixing level. [7..0]: LFE channel input into Right surround channel output mixing level. [15..8]: Bass Sum into Right surround channel output mixing level.
Default = 0xFFFF (Mute, Mute)
BM_C2C_LEVEL
0xB2
2 Bytes
Center channel input into Center channel pass-through mixing level register. Table A-2 shows the relations between the register value and mixing level. [7..0]: Center channel input into Center channel pass-through mixing level. [15..8]: Not Used.
Default = 0x0024 ((+) 0dB)
BM_LFESUM2C_LEVEL
0xB3
2 Bytes
LFE channel and Bass Sum into Center channel output mixing level register. Table A-2 shows the relations between the register value and mixing level. [7..0]: LFE channel input into Center channel output mixing level. [15..8]: Bass Sum into Center channel output mixing level.
Default = 0xFFFF (Mute, Mute)
BM_FILTER_SHIFT
0xB4
2 Bytes
Bass Management LPF shifting value for scaling. [4..0]: Bass Sum low-pass filter shifting value. [7..5]: Not Used. [12..8]: Reserved. [15..13]: Not Used.
Default = 0x0505
BM_EQ_TONE_SEQ_SEL
0xB5
2 Bytes
Equalizer, Tone control, Bass Management sequence selection register. [1..0]: Equalizer, Tone control, Bass Management sequence selector. "00" = Equalizer "01" = Tone control Tone control Bass Management. Equalizer. Tone control.
Bass Management).
Bass Management Equalizer
Tone control
"10" = Bass Management
Default = "00" (Equalizer
[15..2]: Not Used.
Default = 0x0000
Copyright (c) 2000-2003, Pulsus Technologies Inc.
25
2003 REV1.2
PULSUS
Register Name Address Word Length Description
PS9702B
Output Channel Mapping Configuration Registers
OUT_CH_MAPPING1
0xB6
2 Bytes
Internal processing channel into output channel Mapping Register1. "0" : Left channel "1" : Right channel "2" : Left surround channel "3" : Right surround channel "4" : Subwoofer channel "5" : Center channel "6", "7" : Mute channel [2:0]: Internal processing channel which is linked to Output channel 1. [3]: Not Used. [6:4]: Internal processing channel which is linked to Output channel 2. [7]: Not Used. [10:8]: Internal processing channel which is linked to Output channel 3. [11]: Not Used. [14:12]: Internal processing channel which is linked to Output channel 4. [15]: Not Used.
Default = 0x3210
OUT_CH_MAPPING2
0xB7
2 Bytes
Internal processing channel into output channel Mapping Register2. [2:0]: Internal processing channel which is linked to Output channel 6. [3]: Not Used. [6:4]: Internal processing channel which is linked to Output channel 5. [15:7]: Not Used.
Default = 0x0054
REC_SOURCE_SEL
0xB8
2 Bytes
Source for Record output selection register. [0]: Source for Record output. "0"=Left and Right channel of mixer output. "1"=Left and Right channel of mixer input. [15:1]: Not Used.
Default = 0x0000 (mixer output)
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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2003 REV1.2
PULSUS
Register Name Address Word Length Description
PS9702B
Coefficient for Primary Equalizing Filter Registers
P_EQ0_A1
0xC0
3 Bytes
-A1 coefficient for Primary Equalizing filter 0. The filter is a bi-quad filter. A0 coefficient is fixed at value 1. H(z) = (B0 + B1*z-1 + B2*z-2) / (1 + A1*z-1 + A2*z-2) Sampling Frequency of the filter is 192KHz. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x3F89D8 (120~500Hz Band pass filter)
P_EQ0_A2
0xC1
3 Bytes
-A2 coefficient for Primary Equalizing filter 0. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0xE07595 (120~500Hz Band pass filter)
P_EQ0_B0
0xC2
3 Bytes
B0 coefficient for Primary Equalizing filter 0. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x003B4F (120~500Hz Band pass filter)
P_EQ0_B1
0xC3
3 Bytes
B1 coefficient for Primary Equalizing filter 0. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000 (120~500Hz Band pass filter)
P_EQ0_B2
0xC4
3 Bytes
B2 coefficient for Primary Equalizing filter 0. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0xFFC4B1 (120~500Hz Band pass filter)
P_EQ1_A1
0xC5
3 Bytes
-A1 coefficient for Primary Equalizing filter 1. The filter is a bi-quad filter. A0 coefficient is fixed at value 1. H(z) = (B0 + B1*z-1 + B2*z-2) / (1 + A1*z-1 + A2*z-2) Sampling Frequency of the filter is 192KHz. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x3E66D9 (500~2KHz Band pass filter)
P_EQ1_A2
0xC6
3 Bytes
-A2 coefficient for Primary Equalizing filter 1. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0xE19098 (500~2KHz Band pass filter)
P_EQ1_B0
0xC7
3 Bytes
B0 coefficient for Primary Equalizing filter 1. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x00C894 (500~2KHz Band pass filter)
P_EQ1_B1
0xC8
3 Bytes
B1 coefficient for Primary Equalizing filter 1. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000 (500~2KHz Band pass filter)
P_EQ1_B2
0xC9
3 Bytes
B2 coefficient for Primary Equalizing filter 1. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0xFF376C (500~2KHz Band pass filter)
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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Register Name Address Word Length Description
PS9702B
P_EQ2_A1
0xCA
3 Bytes
-A1 coefficient for Primary Equalizing filter 2. The filter is a bi-quad filter. A0 coefficient is fixed at value 1. H(z) = (B0 + B1*z-1 + B2*z-2) / (1 + A1*z-1 + A2*z-2) Sampling Frequency of the filter is 192KHz. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x3995F1 (2K~8KHz Band pass filter)
P_EQ2_A2
0xCB
3 Bytes
-A2 coefficient for Primary Equalizing filter 2. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0xE5EA70 (2K~8KHz Band pass filter)
P_EQ2_B0
0xCC
3 Bytes
B0 coefficient for Primary Equalizing filter 2. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x02F53E (2K~8KHz Band pass filter)
P_EQ2_B1
0xCD
3 Bytes
B1 coefficient for Primary Equalizing filter 2. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000 (2K~8KHz Band pass filter)
P_EQ2_B2
0xCE
3 Bytes
B2 coefficient for Primary Equalizing filter 2. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0xFD0AC2 (2K~8KHz Band pass filter)
P_EQ3_A1
0xCF
3 Bytes
-A1 coefficient for Primary Equalizing filter 3. The filter is a bi-quad filter. A0 coefficient is fixed at value 1. H(z) = (B0 + B1*z-1 + B2*z-2) / (1 + A1*z-1 + A2*z-2) Sampling Frequency of the filter is 192KHz. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x2CF124 (8K~24KHz Band pass filter)
P_EQ3_A2
0xD0
3 Bytes
-A2 coefficient for Primary Equalizing filter 3. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0xEDDFAE (8K~24KHz Band pass filter)
P_EQ3_B0
0xD1
3 Bytes
B0 coefficient for Primary Equalizing filter 3. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x06EFD7 (8K~24KHz Band pass filter)
P_EQ3_B1
0xD2
3 Bytes
B1 coefficient for Primary Equalizing filter 3. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000 (8K~24KHz Band pass filter)
P_EQ3_B2
0xD3
3 Bytes
B2 coefficient for Primary Equalizing filter 3. 3.21 format (3 bits for the integer part and 21 bits for the fractional part). This register is not readable.
Default = 0xF91029 (8K~24KHz Band pass filter)
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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Register Name Address Word Length Description
PS9702B
Coefficient for Secondary Equalizing Filter Registers
S_EQ0_A1
0xD4
3 Bytes
-A1 coefficient for Secondary Equalizing filter 0. The filter is a bi-quad filter. A0 coefficient is fixed at value 1. H(z) = (B0 + B1*z-1 + B2*z-2) / (1 + A1*z-1 + A2*z-2) Sampling Frequency of the filter is 192KHz. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ0_A2
0xD5
3 Bytes
-A2 coefficient for Secondary Equalizing filter 0. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ0_B0
0xD6
3 Bytes
B0 coefficient for Secondary Equalizing filter 0. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ0_B1
0xD7
3 Bytes
B1 coefficient for Secondary Equalizing filter 0. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ0_B2
0xD8
3 Bytes
B2 coefficient for Secondary Equalizing filter 0. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ1_A1
0xD9
3 Bytes
-A1 coefficient for Secondary Equalizing filter 1. The filter is a bi-quad filter. A0 coefficient is fixed at value 1. H(z) = (B0 + B1*z-1 + B2*z-2) / (1 + A1*z-1 + A2*z-2) Sampling Frequency of the filter is 192KHz. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ1_A2
0xDA
3 Bytes
-A2 coefficient for Secondary Equalizing filter 1. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ1_B0
0xDB
3 Bytes
B0 coefficient for Secondary Equalizing filter 1. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ1_B1
0xDC
3 Bytes
B1 coefficient for Secondary Equalizing filter 1. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ1_B2
0xDD
3 Bytes
B2 coefficient for Secondary Equalizing filter 1. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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Register Name Address Word Length Description
PS9702B
S_EQ2_A1
0xDE
3 Bytes
-A1 coefficient for Secondary Equalizing filter 2. The filter is a bi-quad filter. A0 coefficient is fixed at value 1. H(z) = (B0 + B1*z-1 + B2*z-2) / (1 + A1*z-1 + A2*z-2) Sampling Frequency of the filter is 192KHz. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ2_A2
0xDF
3 Bytes
-A2 coefficient for Secondary Equalizing filter 2. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ2_B0
0xE0
3 Bytes
B0 coefficient for Secondary Equalizing filter 2. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ2_B1
0xE1
3 Bytes
B1 coefficient for Secondary Equalizing filter 2. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ2_B2
0xE2
3 Bytes
B2 coefficient for Secondary Equalizing filter 2. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ3_A1
0xE3
3 Bytes
-A1 coefficient for Secondary Equalizing filter 3. The filter is a bi-quad filter. A0 coefficient is fixed at value 1. H(z) = (B0 + B1*z-1 + B2*z-2) / (1 + A1*z-1 + A2*z-2) Sampling Frequency of the filter is 192KHz. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ3_A2
0xE4
3 Bytes
-A2 coefficient for Secondary Equalizing filter 3. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ3_B0
0xE5
3 Bytes
B0 coefficient for Secondary Equalizing filter 3. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ3_B1
0xE6
3 Bytes
B1 coefficient for Secondary Equalizing filter 3. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
S_EQ3_B2
0xE7
3 Bytes
B2 coefficient for Secondary Equalizing filter 3. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000000
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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Register Name Address Word Length Description
PS9702B
Coefficient for Tone Control Filter Registers
BASS_LPF_A1
0xE8
3 Bytes
-A1 coefficient for Bass Low pass filter. The filter is a 1st order filter. A0 coefficient is fixed at value 1. H(z) = (B0 + B1*z-1) / (1 + A1*z-1) Sampling Frequency of the filter is 192KHz. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x1FCA6E (200Hz Low pass filter)
BASS_LPF_B0
0xE9
3 Bytes
B0 coefficient for Bass Low pass filter. B1 coefficient is equal to B0. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x001AC8 (200Hz Low pass filter)
TREBLE_HPF_A1
0xEA
3 Bytes
-A1 coefficient for Treble High pass filter. The filter is a 1st order filter. A0 coefficient is fixed at value 1. H(z) = (B0 + B1*z-1) / (1 + A1*z-1) Sampling Frequency of the filter is 192KHz. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x1A462C (6KHz High pass filter)*
* Above default value is not device default value. It is recommended default value. The PS9702B has erroneous default values of treble filter coefficient registers. In real device, 0xEA register has "0x1D2316" default value and 0xEB register has "0x1A462C" default value. If one wants to use the treble function, 0xEA and 0xEB register must be initialized as the above recommended values. TREBLE_HPF_B0 0xEB 3 Bytes B0 coefficient for Treble High pass filter. B1 coefficient is equal to -B0. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x1D2316 (6KHz High pass filter)*
* Above default value is not device default value. It is recommended default value. The PS9702B has erroneous default values of treble filter coefficient registers. In real device, 0xEA register has "0x1D2316" default value and 0xEB register has "0x1A462C" default value. If one wants to use the treble function, 0xEA and 0xEB register must be initialized as the above recommended values.
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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Register Name Address Word Length Description
PS9702B
Coefficient for Bass Management Low Pass Filter Registers
BM_LPF_A1
0xEC
3 Bytes
-A1 coefficient for Bass Management Low pass filter. The filter is an equally cascaded bi-quad filter (4th order filter). A0 coefficient is fixed at value 1. Sampling Frequency of the filter is 192KHz. H(z) = (B0 + B1*z-1 + B2*z-2)2 / (1 + A1*z-1 + A2*z-2)2 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x3FD273 (120Hz Low pass filter)
BM_LPF_A2
0xED
3 Bytes
-A2 coefficient for Bass Management Low pass filter. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0xE02D6D (120Hz Low pass filter)
BM_LPF_B0
0xEE
3 Bytes
B0 coefficient for Bass Management Low pass filter. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000008 (120Hz Low pass filter)
BM_LPF_B1
0xEF
3 Bytes
B1 coefficient for Bass Management Low pass filter. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000010 (120Hz Low pass filter)
BM_LPF_B2
0xF0
3 Bytes
B2 coefficient for Bass Management Low pass filter. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x000008 (120Hz Low pass filter)
Coefficient for Bass Management High Pass Filter Registers
BM_HPF_A1
0xF1
3 Bytes
-A1 coefficient for Bass Management High pass filter. The filter is a bi-quad filter. A0 coefficient is fixed at value 1. H(z) = (B0 + B1*z-1 + B2*z-2) / (1 + A1*z-1 + A2*z-2) Sampling Frequency of the filter is 192KHz. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x3FD273 (120Hz High pass filter)
BM_HPF_A2
0xF2
3 Bytes
-A2 coefficient for Bass Management High pass filter. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0xE02D6D (120Hz High pass filter)
BM_HPF_B0
0xF3
3 Bytes
B0 coefficient for Bass Management High pass filter. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x1FE93F (120Hz High pass filter)
BM_HPF_B1
0xF4
3 Bytes
B1 coefficient for Bass Management High pass filter. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0xC02D82 (120Hz High pass filter)
BM_HPF_B2
0xF5
3 Bytes
B2 coefficient for Bass Management High pass filter. 3.21 format (3 bits for the integer part and 21 bits for the fractional part).
Default = 0x1FE93F (120Hz High pass filter)
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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AC Characteristics
1. I2C Control Interface Timing
Parameter SCL Clock Frequency Start Condition Hold Time (Prior to first clock pulse) Clock Low Time Clock High Time Setup Time For Repeated Start Condition Data Hold Time Data Set-Up Time Rise Time of both SDA and SCL Falling Time of both SDA and SCL Setup Time for Stop Condition THDST TLOW THIGH TSUST THDD TSUD TR TF TSUSP 200 200 400 400 200 0 100 Symbol Min -
PS9702B
Max 800
Units kHz ns ns ns ns ns ns
300 300
ns ns ns
TR Start SDA Repeated Start
TF Stop
SCL
THDST THDST TLOW THIGH THDD TSUD TSUST TR TF TSUSP
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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2. SPI Write Timing
Parameter Start Condition Hold Time Clock High Time Clock Low Time SI Setup Time to SCK Data Hold Time Falling Time of both SI and SCK Rising Time of both SI and SCK Setup Time for Stop Condition Symbol THDST THIGH TLOW TSUD THDD TDF TDR TSUSP 200 Min 200 400 400 100 0 -
PS9702B
Max
Units ns ns ns ns ns
300 300
ns ns ns
TR THDST /CS THIGH TLOW TDF
TF TSUSP TDR
SCK
SI
SO
THDD TSUD
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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3. SPI Read Timing
Parameter Start Condition Hold Time Clock High Time Clock Low Time SO Delay time for Valid Data Falling Time of both SO and SCK Rising Time of both SO and SCK Setup Time for Stop Condition Symbol THDST THIGH TLOW TD TDF TDR TSUSP 200 Min 200 400 400 100 -
PS9702B
Max
Units ns ns ns ns
300 300
ns ns ns
TR THDST /CS THIGH TLOW TD
TF TSUSP
SCK
SI
SO
TDR
TDF
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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4. I2S Data Interface Timing
Parameter Data Holding Time Data Setup Time Clock High Time Clock Low Time Rising Time of SCK (Slave Mode) Falling Time of SCK (Slave Mode) Rising Time of SCK (Master Mode) Falling Time of SCK (Master Mode) Delay until valid Data Symbol THDIS TSUIS THIGH TLOW TRISS TFISS TRISM TFISM TDD 20 3 3 Min 25 25 80 80 180 180 Typ
PS9702B
Max
Units ns ns ns ns
20 20 5 5 40
ns ns ns ns ns
Slave Mode
THIGH TLOW TRISS TFISS
LRCK
BCK
SDIN
MSB
LSB
MSB
TSUIS
THDIS
Master Mode
THIGH TLOW TRISM TFISM
LRCK
BCK
SDIN
MSB
LSB
MSB
TDD
BCK : Positive Edge Enable
36 2003 REV1.2
Copyright (c) 2000-2003, Pulsus Technologies Inc.
PULSUS
Package Dimensions
PS9702B
Unit : mm
16 0.2 14 0.1 75 51
76
50
14 0.1 INDEX 100 26 1 0.5 0.22
0.05
25
1.6 m ax
1.4 0.1
0.15 0.05 0o 7o 0.6 1
0.1
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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GainGain-Register Value Table
Table A-1. Volume Gain Values
Gain (dB) 24.0 23.5 23.0 22.5 22.0 21.5 21.0 20.5 20.0 19.5 19.0 18.5 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 Register Value 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C Gain (dB) 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5 -18.0 -18.5 -19.0 -19.5 -20.0 -20.5 Register Value 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 Gain (dB) -21.0 -21.5 -22.0 -22.5 -23.0 -23.5 -24.0 -24.5 -25.0 -25.5 -26.0 -26.5 -27.0 -27.5 -28.0 -28.5 -29.0 -29.5 -30.0 -30.5 -31.0 -31.5 -32.0 -32.5 -33.0 -33.5 -34.0 -34.5 -35.0 -35.5 -36.0 -36.5 -37.0 -37.5 -38.0 -38.5 -39.0 -39.5 -40.0 -40.5 -41.0 -41.5 -42.0 -42.5 -43.0 38 Register Value 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 Gain (dB) -43.5 -44.0 -44.5 -45.0 -45.5 -46.0 -46.5 -47.0 -47.5 -48.0 -48.5 -49.0 -49.5 -50.0 -50.5 -51.0 -51.5 -52.0 -52.5 -53.0 -53.5 -54.0 -54.5 -55.0 -55.5 -56.0 -56.5 -57.0 -57.5 -58.0 -58.5 -59.0 -59.5 -60.0 -60.5 -61.0 -61.5 -62.0 -62.5 -63.0 -63.5 -64.0 -64.5 -65.0 -65.5 Register Value 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3
PS9702B
Appendix A
Gain (dB) -66.0 -66.5 -67.0 -67.5 -68.0 -68.5 -69.0 -69.5 -70.0 Mute | Mute
Register Value 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD | 0xFF
Copyright (c) 2000-2003, Pulsus Technologies Inc.
2003 REV1.2
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Table A-2. Mixer Gain Values Signal Polarity + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Gain (dB) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 Register Value 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 Signal Polarity + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Gain (dB) -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5 -18.0 -18.5 -19.0 -19.5 -20.0 -20.5 -21.0 -21.5 -22.0 -22.5 Register Value 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 Signal Polarity + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Gain (dB)
PS9702B
Register Value 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7F
-23.0 -23.5 -24.0 -24.5 -25.0 -25.5 -26.0 -26.5 -27.0 -27.5 -28.0 -28.5 -29.0 -29.5 -30.0 -30.5 -31.0 -31.5 -32.0 -32.5 -33.0 -33.5 -34.0 -34.5 -35.0 -35.5 -36.0 -36.5 -37.0 -37.5 -38.0 -38.5 -39.0 -39.5 -40.0 -40.5 -41.0 -41.5 -42.0 Mute Mute
Copyright (c) 2000-2003, Pulsus Technologies Inc.
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2003 REV1.2
PULSUS
Table A-2. Mixer Gain Values (Continued) Signal Polarity Gain (dB) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 Register Value 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0XA1 0XA2 0XA3 0XA4 0xA5 0xA6 0xA7 0xA8 Signal Polarity Gain (dB) -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 -9.5 -10.0 -10.5 -11.0 -11.5 -12.0 -12.5 -13.0 -13.5 -14.0 -14.5 -15.0 -15.5 -16.0 -16.5 -17.0 -17.5 -18.0 -18.5 -19.0 -19.5 -20.0 -20.5 -21.0 -21.5 -22.0 -22.5 Register Value 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 Signal Polarity Gain (dB) -23.0
PS9702B
Register Value 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFF
-23.5 -24.0 -24.5 -25.0 -25.5 -26.0 -26.5 -27.0 -27.5 -28.0 -28.5 -29.0 -29.5 -30.0 -30.5 -31.0 -31.5 -32.0 -32.5 -33.0 -33.5 -34.0 -34.5 -35.0 -35.5 -36.0 -36.5 -37.0 -37.5 -38.0 -38.5 -39.0 -39.5 -40.0 -40.5 -41.0 -41.5 -42.0 Mute Mute
Copyright (c) 2000-2003, Pulsus Technologies Inc.
40
2003 REV1.2
PULSUS
Table A-3. EQ, Treble, Bass Gain Values
Gain (dB) 15.0 14.0 13.0 12.0 11.0 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 Register Value 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 Gain (dB) -1.0 -2.0 -3.0 -4.0 -5.0 -6.0 -7.0 -8.0 -9.0 -10.0 -11.0 -12.0 -13.0 -14.0 -15.0 Register Value 0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11
PS9702B
Copyright (c) 2000-2003, Pulsus Technologies Inc.
41
2003 REV1.2

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